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Artnet-LED/PM Artnet LED DMX.kicad_pcb...

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added components
2020-09-09 20:10:56 +02:00
(kicad_pcb (version 20171130) (host pcbnew "(5.1.6-0-10_14)")
initial commit
2020-08-31 13:01:17 +02:00
(general
(thickness 1.6)
initial commit
2020-09-09 10:09:40 +02:00
(drawings 7)
wired everything
2020-09-09 22:16:18 +02:00
(tracks 329)
initial commit
2020-08-31 13:01:17 +02:00
(zones 0)
added components
2020-09-09 20:10:56 +02:00
(modules 24)
wired everything
2020-09-09 22:16:18 +02:00
(nets 71)
initial commit
2020-08-31 13:01:17 +02:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user hide)
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
(44 Edge.Cuts user)
(45 Margin user hide)
(46 B.CrtYd user hide)
(47 F.CrtYd user hide)
(48 B.Fab user hide)
(49 F.Fab user hide)
)
(setup
added components
2020-09-09 20:10:56 +02:00
(last_trace_width 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(user_trace_width 0.5)
initial commit
2020-08-31 13:01:17 +02:00
(user_trace_width 0.75)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(via_size 0.8)
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(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
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(edge_width 0.05)
(segment_width 0.2)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 2.1 2.1)
(pad_drill 1.1)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
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(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "export/"))
)
(net 0 "")
(net 1 "Net-(J1-Pad1)")
(net 2 "Net-(J1-Pad2)")
(net 3 "Net-(J1-Pad3)")
(net 4 "Net-(J1-Pad4)")
(net 5 "Net-(J1-Pad5)")
(net 6 "Net-(J1-Pad6)")
(net 7 "Net-(J1-Pad7)")
(net 8 "Net-(J1-Pad8)")
(net 9 "Net-(J1-Pad9)")
(net 10 "Net-(J1-Pad10)")
(net 11 "Net-(J1-Pad11)")
(net 12 "Net-(J1-Pad12)")
(net 13 "Net-(J7-Pad1)")
(net 14 "Net-(J8-Pad1)")
(net 15 "Net-(J9-Pad1)")
(net 16 "Net-(J10-Pad1)")
(net 17 "Net-(J10-Pad4)")
(net 18 "Net-(J11-Pad3)")
(net 19 "Net-(J11-Pad2)")
(net 20 "Net-(J12-Pad3)")
(net 21 "Net-(J12-Pad2)")
(net 22 "Net-(J13-Pad3)")
(net 23 "Net-(J13-Pad2)")
(net 24 "Net-(J14-Pad3)")
(net 25 "Net-(J14-Pad2)")
(net 26 "Net-(J17-Pad13)")
(net 27 "Net-(J17-Pad14)")
(net 28 "Net-(J17-Pad15)")
(net 29 "Net-(J17-Pad16)")
(net 30 "Net-(J17-Pad17)")
(net 31 "Net-(J17-Pad18)")
(net 32 "Net-(J17-Pad19)")
(net 33 "Net-(J17-Pad20)")
(net 34 "Net-(J17-Pad21)")
(net 35 "Net-(J17-Pad22)")
(net 36 "Net-(J17-Pad23)")
(net 37 "Net-(J18-Pad23)")
(net 38 "Net-(J18-Pad22)")
(net 39 "Net-(J18-Pad21)")
(net 40 "Net-(J18-Pad20)")
(net 41 "Net-(J18-Pad19)")
(net 42 "Net-(J18-Pad18)")
(net 43 "Net-(J18-Pad17)")
(net 44 "Net-(J18-Pad16)")
(net 45 "Net-(J18-Pad15)")
(net 46 "Net-(J18-Pad14)")
(net 47 "Net-(J18-Pad13)")
wired everything
2020-09-09 22:16:18 +02:00
(net 48 "Net-(J18-Pad10)")
(net 49 "Net-(J18-Pad9)")
(net 50 "Net-(J18-Pad8)")
(net 51 "Net-(J18-Pad7)")
(net 52 "Net-(J18-Pad6)")
(net 53 "Net-(J18-Pad5)")
(net 54 "Net-(J18-Pad4)")
(net 55 "Net-(J18-Pad3)")
(net 56 "Net-(J18-Pad2)")
(net 57 "Net-(J18-Pad1)")
(net 58 +5V)
(net 59 GND)
(net 60 "Net-(J6-Pad2)")
(net 61 "Net-(J5-Pad11)")
(net 62 "Net-(J5-Pad10)")
(net 63 "Net-(J5-Pad9)")
(net 64 "Net-(J5-Pad8)")
(net 65 "Net-(J5-Pad7)")
(net 66 "Net-(J5-Pad6)")
(net 67 "Net-(J5-Pad5)")
(net 68 "Net-(J5-Pad4)")
(net 69 "Net-(C1-Pad1)")
(net 70 "Net-(J18-Pad12)")
initial commit
2020-08-31 13:01:17 +02:00
(net_class Default "Dies ist die voreingestellte Netzklasse."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +5V)
(add_net GND)
added components
2020-09-09 20:10:56 +02:00
(add_net "Net-(C1-Pad1)")
initial commit
2020-08-31 13:01:17 +02:00
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J1-Pad10)")
(add_net "Net-(J1-Pad11)")
(add_net "Net-(J1-Pad12)")
(add_net "Net-(J1-Pad2)")
(add_net "Net-(J1-Pad3)")
(add_net "Net-(J1-Pad4)")
(add_net "Net-(J1-Pad5)")
(add_net "Net-(J1-Pad6)")
(add_net "Net-(J1-Pad7)")
(add_net "Net-(J1-Pad8)")
(add_net "Net-(J1-Pad9)")
(add_net "Net-(J10-Pad1)")
(add_net "Net-(J10-Pad4)")
(add_net "Net-(J11-Pad2)")
(add_net "Net-(J11-Pad3)")
(add_net "Net-(J12-Pad2)")
(add_net "Net-(J12-Pad3)")
(add_net "Net-(J13-Pad2)")
(add_net "Net-(J13-Pad3)")
(add_net "Net-(J14-Pad2)")
(add_net "Net-(J14-Pad3)")
(add_net "Net-(J17-Pad13)")
(add_net "Net-(J17-Pad14)")
(add_net "Net-(J17-Pad15)")
(add_net "Net-(J17-Pad16)")
(add_net "Net-(J17-Pad17)")
(add_net "Net-(J17-Pad18)")
(add_net "Net-(J17-Pad19)")
(add_net "Net-(J17-Pad20)")
(add_net "Net-(J17-Pad21)")
(add_net "Net-(J17-Pad22)")
(add_net "Net-(J17-Pad23)")
(add_net "Net-(J18-Pad1)")
(add_net "Net-(J18-Pad10)")
wired everything
2020-09-09 22:16:18 +02:00
(add_net "Net-(J18-Pad12)")
initial commit
2020-08-31 13:01:17 +02:00
(add_net "Net-(J18-Pad13)")
(add_net "Net-(J18-Pad14)")
(add_net "Net-(J18-Pad15)")
(add_net "Net-(J18-Pad16)")
(add_net "Net-(J18-Pad17)")
(add_net "Net-(J18-Pad18)")
(add_net "Net-(J18-Pad19)")
(add_net "Net-(J18-Pad2)")
(add_net "Net-(J18-Pad20)")
(add_net "Net-(J18-Pad21)")
(add_net "Net-(J18-Pad22)")
(add_net "Net-(J18-Pad23)")
(add_net "Net-(J18-Pad3)")
(add_net "Net-(J18-Pad4)")
(add_net "Net-(J18-Pad5)")
(add_net "Net-(J18-Pad6)")
(add_net "Net-(J18-Pad7)")
(add_net "Net-(J18-Pad8)")
(add_net "Net-(J18-Pad9)")
initial commit
2020-09-09 10:09:40 +02:00
(add_net "Net-(J5-Pad10)")
(add_net "Net-(J5-Pad11)")
(add_net "Net-(J5-Pad4)")
(add_net "Net-(J5-Pad5)")
(add_net "Net-(J5-Pad6)")
(add_net "Net-(J5-Pad7)")
(add_net "Net-(J5-Pad8)")
(add_net "Net-(J5-Pad9)")
initial commit
2020-08-31 13:01:17 +02:00
(add_net "Net-(J6-Pad2)")
(add_net "Net-(J7-Pad1)")
(add_net "Net-(J8-Pad1)")
(add_net "Net-(J9-Pad1)")
added components
2020-09-09 20:10:56 +02:00
)
(module CRCW08054K70FKEAC:RESC2012X60N (layer F.Cu) (tedit 5F58A022) (tstamp 5F593EEF)
wired everything
2020-09-09 22:16:18 +02:00
(at 157.861 117.795 270)
added components
2020-09-09 20:10:56 +02:00
(descr 0805-ren2)
(tags Resistor)
(path /6055B232)
(attr smd)
(fp_text reference R1 (at 0 0 90) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_text value CRCW08054K70FKEAC (at 0 0 90) (layer F.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_line (start -1.65 -1) (end 1.65 -1) (layer Dwgs.User) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.65 -1) (end 1.65 1) (layer Dwgs.User) (width 0.05))
(fp_line (start 1.65 1) (end -1.65 1) (layer Dwgs.User) (width 0.05))
(fp_line (start -1.65 1) (end -1.65 -1) (layer Dwgs.User) (width 0.05))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 -0.625) (end 1 0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 0.625) (end -1 0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start -1 0.625) (end -1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 0 -0.525) (end 0 0.525) (layer F.SilkS) (width 0.2))
added components
2020-09-09 20:10:56 +02:00
(pad 2 smd rect (at 0.95 0 270) (size 0.9 1.45) (layers F.Cu F.Paste F.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 0.9 1.45) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(J18-Pad15)"))
)
(module Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm (layer F.Cu) (tedit 5E476F32) (tstamp 5F590A65)
(at 149.86 117.7875 270)
(descr "TSSOP, 20 Pin (JEDEC MO-153 Var AC https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator ipc_gullwing_generator.py")
(tags "TSSOP SO")
(path /60B14C8C)
(attr smd)
(fp_text reference U1 (at 0 -4.2 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TXS0108EPW (at 0 4.2 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 3.85 -3.5) (end -3.85 -3.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.85 3.5) (end 3.85 -3.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.85 3.5) (end 3.85 3.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.85 -3.5) (end -3.85 3.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.2 -2.25) (end -1.2 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start -2.2 3.25) (end -2.2 -2.25) (layer F.Fab) (width 0.1))
(fp_line (start 2.2 3.25) (end -2.2 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 2.2 -3.25) (end 2.2 3.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.2 -3.25) (end 2.2 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 0 -3.385) (end -3.6 -3.385) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -3.385) (end 2.2 -3.385) (layer F.SilkS) (width 0.12))
(fp_line (start 0 3.385) (end -2.2 3.385) (layer F.SilkS) (width 0.12))
(fp_line (start 0 3.385) (end 2.2 3.385) (layer F.SilkS) (width 0.12))
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 20 smd roundrect (at 2.8625 -2.925 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 68 "Net-(J5-Pad4)"))
added components
2020-09-09 20:10:56 +02:00
(pad 19 smd roundrect (at 2.8625 -2.275 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
added components
2020-09-09 20:10:56 +02:00
(pad 18 smd roundrect (at 2.8625 -1.625 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 67 "Net-(J5-Pad5)"))
added components
2020-09-09 20:10:56 +02:00
(pad 17 smd roundrect (at 2.8625 -0.975 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 66 "Net-(J5-Pad6)"))
added components
2020-09-09 20:10:56 +02:00
(pad 16 smd roundrect (at 2.8625 -0.325 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 65 "Net-(J5-Pad7)"))
added components
2020-09-09 20:10:56 +02:00
(pad 15 smd roundrect (at 2.8625 0.325 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 64 "Net-(J5-Pad8)"))
added components
2020-09-09 20:10:56 +02:00
(pad 14 smd roundrect (at 2.8625 0.975 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 63 "Net-(J5-Pad9)"))
added components
2020-09-09 20:10:56 +02:00
(pad 13 smd roundrect (at 2.8625 1.625 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 62 "Net-(J5-Pad10)"))
added components
2020-09-09 20:10:56 +02:00
(pad 12 smd roundrect (at 2.8625 2.275 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 61 "Net-(J5-Pad11)"))
added components
2020-09-09 20:10:56 +02:00
(pad 11 smd roundrect (at 2.8625 2.925 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 10 smd roundrect (at -2.8625 2.925 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 45 "Net-(J18-Pad15)"))
(pad 9 smd roundrect (at -2.8625 2.275 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 37 "Net-(J18-Pad23)"))
(pad 8 smd roundrect (at -2.8625 1.625 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 38 "Net-(J18-Pad22)"))
(pad 7 smd roundrect (at -2.8625 0.975 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 39 "Net-(J18-Pad21)"))
(pad 6 smd roundrect (at -2.8625 0.325 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 40 "Net-(J18-Pad20)"))
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(net 41 "Net-(J18-Pad19)"))
(pad 4 smd roundrect (at -2.8625 -0.975 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 42 "Net-(J18-Pad18)"))
(pad 3 smd roundrect (at -2.8625 -1.625 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 43 "Net-(J18-Pad17)"))
(pad 2 smd roundrect (at -2.8625 -2.275 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
wired everything
2020-09-09 22:16:18 +02:00
(net 69 "Net-(C1-Pad1)"))
added components
2020-09-09 20:10:56 +02:00
(pad 1 smd roundrect (at -2.8625 -2.925 270) (size 1.475 0.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 44 "Net-(J18-Pad16)"))
(model ${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-20_4.4x6.5mm_P0.65mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module C0805X106K8RACAUTO:CAPC2012X100N (layer F.Cu) (tedit 5F58965D) (tstamp 5F590313)
wired everything
2020-09-09 22:16:18 +02:00
(at 57.023 44.45 90)
added components
2020-09-09 20:10:56 +02:00
(descr 0805-ren4)
(tags Capacitor)
(path /61AE490B)
(attr smd)
wired everything
2020-09-09 22:16:18 +02:00
(fp_text reference C4 (at 0 0 90) (layer F.SilkS)
added components
2020-09-09 20:10:56 +02:00
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
wired everything
2020-09-09 22:16:18 +02:00
(fp_text value C0805X106K8RACAUTO (at 0 0 90) (layer F.SilkS) hide
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2020-09-09 20:10:56 +02:00
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
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wired everything
2020-09-09 22:16:18 +02:00
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(net 69 "Net-(C1-Pad1)"))
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(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
)
(module C0805C104K5RAC7411:CAPC2012X88N (layer F.Cu) (tedit 5F5892AE) (tstamp 5F590305)
wired everything
2020-09-09 22:16:18 +02:00
(at 50.8 44.45 270)
added components
2020-09-09 20:10:56 +02:00
(descr C0805C104K5RAC7411-+-+)
(tags Capacitor)
(path /61AE12C5)
(attr smd)
wired everything
2020-09-09 22:16:18 +02:00
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added components
2020-09-09 20:10:56 +02:00
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wired everything
2020-09-09 22:16:18 +02:00
(fp_text value C0805C104K5RAC7411 (at 0 0 90) (layer F.SilkS) hide
added components
2020-09-09 20:10:56 +02:00
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_line (start -1.46 -0.89) (end 1.46 -0.89) (layer Dwgs.User) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.46 -0.89) (end 1.46 0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start 1.46 0.89) (end -1.46 0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start -1.46 0.89) (end -1.46 -0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start -1 -0.625) (end 1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 -0.625) (end 1 0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 0.625) (end -1 0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start -1 0.625) (end -1 -0.625) (layer Dwgs.User) (width 0.1))
(pad 2 smd rect (at 0.8 0 270) (size 1.02 1.47) (layers F.Cu F.Paste F.Mask)
(net 59 GND))
(pad 1 smd rect (at -0.8 0 270) (size 1.02 1.47) (layers F.Cu F.Paste F.Mask)
(net 58 +5V))
added components
2020-09-09 20:10:56 +02:00
)
(module C0805C104K5RAC7411:CAPC2012X88N (layer B.Cu) (tedit 5F5892AE) (tstamp 5F5902F7)
wired everything
2020-09-09 22:16:18 +02:00
(at 141.351 120.866 270)
added components
2020-09-09 20:10:56 +02:00
(descr C0805C104K5RAC7411-+-+)
(tags Capacitor)
(path /61A81CE2)
(attr smd)
(fp_text reference C2 (at 0 0 90) (layer B.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.254)) (justify mirror))
)
(fp_text value C0805C104K5RAC7411 (at 0 0 90) (layer B.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.254)) (justify mirror))
)
(fp_line (start -1.46 0.89) (end 1.46 0.89) (layer Dwgs.User) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.46 0.89) (end 1.46 -0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start 1.46 -0.89) (end -1.46 -0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start -1.46 -0.89) (end -1.46 0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start -1 0.625) (end 1 0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 0.625) (end 1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start -1 -0.625) (end -1 0.625) (layer Dwgs.User) (width 0.1))
added components
2020-09-09 20:10:56 +02:00
(pad 2 smd rect (at 0.8 0 270) (size 1.02 1.47) (layers B.Cu B.Paste B.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 1 smd rect (at -0.8 0 270) (size 1.02 1.47) (layers B.Cu B.Paste B.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
added components
2020-09-09 20:10:56 +02:00
)
(module C0805C104K5RAC7411:CAPC2012X88N (layer B.Cu) (tedit 5F5892AE) (tstamp 5F5902E9)
wired everything
2020-09-09 22:16:18 +02:00
(at 137.922 120.866 270)
added components
2020-09-09 20:10:56 +02:00
(descr C0805C104K5RAC7411-+-+)
(tags Capacitor)
(path /61998171)
(attr smd)
(fp_text reference C1 (at 0 0 90) (layer B.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.254)) (justify mirror))
)
(fp_text value C0805C104K5RAC7411 (at 0 0 90) (layer B.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.254)) (justify mirror))
)
(fp_line (start -1.46 0.89) (end 1.46 0.89) (layer Dwgs.User) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.46 0.89) (end 1.46 -0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start 1.46 -0.89) (end -1.46 -0.89) (layer Dwgs.User) (width 0.05))
(fp_line (start -1.46 -0.89) (end -1.46 0.89) (layer Dwgs.User) (width 0.05))
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(fp_line (start 1 0.625) (end 1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer Dwgs.User) (width 0.1))
(fp_line (start -1 -0.625) (end -1 0.625) (layer Dwgs.User) (width 0.1))
added components
2020-09-09 20:10:56 +02:00
(pad 2 smd rect (at 0.8 0 270) (size 1.02 1.47) (layers B.Cu B.Paste B.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 1 smd rect (at -0.8 0 270) (size 1.02 1.47) (layers B.Cu B.Paste B.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 69 "Net-(C1-Pad1)"))
initial commit
2020-08-31 13:01:17 +02:00
)
initial commit
2020-09-09 10:09:40 +02:00
(module Button_Switch_THT:SW_DIP_SPSTx06_Slide_9.78x17.42mm_W7.62mm_P2.54mm (layer F.Cu) (tedit 5A4E1405) (tstamp 5F4EBE24)
(at 117.475 27.305 90)
(descr "6x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x17.42mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)")
(tags "DIP Switch SPST Slide 7.62mm 300mil")
(path /619A0A26)
(fp_text reference SW1 (at 3.81 -3.42 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SW_DIP_x06 (at 3.81 16.12 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start 8.95 -2.7) (end -1.35 -2.7) (layer F.CrtYd) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 8.95 15.4) (end 8.95 -2.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.35 15.4) (end 8.95 15.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.35 -2.7) (end -1.35 15.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.133333 12.065) (end 3.133333 13.335) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 13.265) (end 3.133333 13.265) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 13.145) (end 3.133333 13.145) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 13.025) (end 3.133333 13.025) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.905) (end 3.133333 12.905) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.785) (end 3.133333 12.785) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.665) (end 3.133333 12.665) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.545) (end 3.133333 12.545) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.425) (end 3.133333 12.425) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.305) (end 3.133333 12.305) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.185) (end 3.133333 12.185) (layer F.SilkS) (width 0.12))
(fp_line (start 5.84 12.065) (end 1.78 12.065) (layer F.SilkS) (width 0.12))
(fp_line (start 5.84 13.335) (end 5.84 12.065) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 13.335) (end 5.84 13.335) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 12.065) (end 1.78 13.335) (layer F.SilkS) (width 0.12))
(fp_line (start 3.133333 9.525) (end 3.133333 10.795) (layer F.SilkS) (width 0.12))
(fp_line (start 1.78 10.725) (end 3.133333 10.725) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.78 10.485) (end 3.133333 10.485) (layer F.SilkS) (width 0.12))
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(fp_line (start 3.133333 1.905) (end 3.133333 3.175) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.78 0.085) (end 3.133333 0.085) (layer F.SilkS) (width 0.12))
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(fp_line (start 8.76 -2.42) (end 8.76 15.12) (layer F.SilkS) (width 0.12))
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(fp_line (start 1.78 10.025) (end 3.133333 10.025) (layer F.Fab) (width 0.1))
(fp_line (start 1.78 9.925) (end 3.133333 9.925) (layer F.Fab) (width 0.1))
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(fp_line (start -0.08 -2.36) (end 8.7 -2.36) (layer F.Fab) (width 0.1))
added components
2020-09-09 20:10:56 +02:00
(fp_text user on (at 5.365 -1.4975 90) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
initial commit
2020-08-31 13:01:17 +02:00
)
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at 7.27 6.35) (layer F.Fab)
(effects (font (size 0.8 0.8) (thickness 0.12)))
)
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wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 6 thru_hole oval (at 0 12.7 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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wired everything
2020-09-09 22:16:18 +02:00
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added components
2020-09-09 20:10:56 +02:00
(pad 5 thru_hole oval (at 0 10.16 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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wired everything
2020-09-09 22:16:18 +02:00
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2020-09-09 20:10:56 +02:00
(pad 4 thru_hole oval (at 0 7.62 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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2020-09-09 22:16:18 +02:00
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2020-09-09 20:10:56 +02:00
(pad 3 thru_hole oval (at 0 5.08 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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2020-09-09 22:16:18 +02:00
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2020-09-09 20:10:56 +02:00
(pad 2 thru_hole oval (at 0 2.54 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
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2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 "Net-(J1-Pad1)"))
(model ${KISYS3DMOD}/Button_Switch_THT.3dshapes/SW_DIP_SPSTx06_Slide_9.78x17.42mm_W7.62mm_P2.54mm.wrl
initial commit
2020-08-31 13:01:17 +02:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
added components
2020-09-09 20:10:56 +02:00
(rotate (xyz 0 0 90))
initial commit
2020-08-31 13:01:17 +02:00
)
)
added components
2020-09-09 20:10:56 +02:00
(module LD1117V33:TO255P460X1020X2008-3P (layer F.Cu) (tedit 5F4CDE42) (tstamp 5F4E4359)
(at 51.435 36.83)
(descr "3-Pin TO-220")
(tags "Integrated Circuit")
(path /5F6D9254)
(fp_text reference VCC3v3 (at 2.54 -1.905) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_text value LD1117V33 (at 0 0) (layer F.SilkS) hide
(effects (font (size 1.27 1.27) (thickness 0.254)))
)
(fp_line (start -2.65 -3.07) (end -2.65 0) (layer F.SilkS) (width 0.2))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 7.75 -3.07) (end -2.65 -3.07) (layer F.SilkS) (width 0.2))
(fp_line (start 7.75 1.53) (end 7.75 -3.07) (layer F.SilkS) (width 0.2))
(fp_line (start -2.65 -1.795) (end -1.375 -3.07) (layer Dwgs.User) (width 0.1))
(fp_line (start -2.65 1.53) (end -2.65 -3.07) (layer Dwgs.User) (width 0.1))
(fp_line (start 7.75 1.53) (end -2.65 1.53) (layer Dwgs.User) (width 0.1))
(fp_line (start 7.75 -3.07) (end 7.75 1.53) (layer Dwgs.User) (width 0.1))
(fp_line (start -2.65 -3.07) (end 7.75 -3.07) (layer Dwgs.User) (width 0.1))
(fp_line (start -2.9 1.78) (end -2.9 -3.32) (layer Dwgs.User) (width 0.05))
(fp_line (start 8 1.78) (end -2.9 1.78) (layer Dwgs.User) (width 0.05))
(fp_line (start 8 -3.32) (end 8 1.78) (layer Dwgs.User) (width 0.05))
(fp_line (start -2.9 -3.32) (end 8 -3.32) (layer Dwgs.User) (width 0.05))
added components
2020-09-09 20:10:56 +02:00
(pad 3 thru_hole circle (at 5.1 0 90) (size 1.98 1.98) (drill 1.32) (layers *.Cu *.Mask F.SilkS)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 2 thru_hole circle (at 2.55 0 90) (size 1.98 1.98) (drill 1.32) (layers *.Cu *.Mask F.SilkS)
wired everything
2020-09-09 22:16:18 +02:00
(net 69 "Net-(C1-Pad1)"))
added components
2020-09-09 20:10:56 +02:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.98 1.98) (drill 1.32) (layers *.Cu *.Mask F.SilkS)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
added components
2020-09-09 20:10:56 +02:00
)
(module Connector_PinSocket_2.54mm:PinSocket_1x24_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A427) (tstamp 5EB87CDB)
(at 116.205 65.405)
(descr "Through hole straight socket strip, 1x24, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x24 2.54mm single row")
(path /5EBEF8A2)
(fp_text reference J17 (at 0 -2.77) (layer F.SilkS)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_text value "CMOD A7 J1" (at 0 61.19) (layer F.Fab)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 59.69) (end -1.27 59.69) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 59.69) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 59.75) (end 1.33 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 60.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 60.2) (end -1.8 60.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 60.2) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at 0 29.21 90) (layer F.Fab)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 19 thru_hole oval (at 0 45.72) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 20 thru_hole oval (at 0 48.26) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 21 thru_hole oval (at 0 50.8) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 22 thru_hole oval (at 0 53.34) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 23 thru_hole oval (at 0 55.88) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(J17-Pad23)"))
(pad 24 thru_hole oval (at 0 58.42) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
added components
2020-09-09 20:10:56 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x24_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C07)
(at 201.93 19.685 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA115E)
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(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX0 DI DE RE RO" (at 3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
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(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
added components
2020-09-09 20:10:56 +02:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 46 "Net-(J18-Pad14)"))
added components
2020-09-09 20:10:56 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
initial commit
2020-08-31 13:01:17 +02:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
added components
2020-09-09 20:10:56 +02:00
(module Connector_PinSocket_2.54mm:PinSocket_2x07_P2.54mm_Horizontal (layer F.Cu) (tedit 5A19A422) (tstamp 5EB8928C)
(at 94.615 30.48 270)
(descr "Through hole angled socket strip, 2x07, 2.54mm pitch, 8.51mm socket length, double cols (from Kicad 4.0.7), script generated")
(tags "Through hole angled socket strip THT 2x07 2.54mm double row")
(path /5EDAE843)
(fp_text reference J6 (at -5.65 -2.77 90) (layer F.SilkS)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_text value LAN8720 (at -5.65 18.01 90) (layer F.Fab)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -12.57 -1.27) (end -5.03 -1.27) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start -5.03 -1.27) (end -4.06 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -4.06 -0.3) (end -4.06 16.51) (layer F.Fab) (width 0.1))
(fp_line (start -4.06 16.51) (end -12.57 16.51) (layer F.Fab) (width 0.1))
(fp_line (start -12.57 16.51) (end -12.57 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0 -0.3) (end -4.06 -0.3) (layer F.Fab) (width 0.1))
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(fp_line (start 0 0.3) (end 0 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 0 2.24) (end -4.06 2.24) (layer F.Fab) (width 0.1))
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(fp_line (start 0 2.84) (end 0 2.24) (layer F.Fab) (width 0.1))
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(fp_line (start 0 5.38) (end 0 4.78) (layer F.Fab) (width 0.1))
(fp_line (start 0 7.32) (end -4.06 7.32) (layer F.Fab) (width 0.1))
(fp_line (start -4.06 7.92) (end 0 7.92) (layer F.Fab) (width 0.1))
(fp_line (start 0 7.92) (end 0 7.32) (layer F.Fab) (width 0.1))
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(fp_line (start 0 10.46) (end 0 9.86) (layer F.Fab) (width 0.1))
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(fp_line (start 0 15.54) (end 0 14.94) (layer F.Fab) (width 0.1))
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(fp_line (start -12.63 -1.33) (end -12.63 16.57) (layer F.SilkS) (width 0.12))
(fp_line (start 1.11 -1.33) (end 1.11 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.11 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.8 -1.75) (end -13.05 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -13.05 -1.75) (end -13.05 17.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -13.05 17.05) (end 1.8 17.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 17.05) (end 1.8 -1.75) (layer F.CrtYd) (width 0.05))
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at -8.315 7.62) (layer F.Fab)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 26 "Net-(J17-Pad13)"))
(pad 2 thru_hole oval (at -2.54 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 60 "Net-(J6-Pad2)"))
added components
2020-09-09 20:10:56 +02:00
(pad 3 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 27 "Net-(J17-Pad14)"))
(pad 4 thru_hole oval (at -2.54 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(J17-Pad23)"))
(pad 5 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 30 "Net-(J17-Pad17)"))
(pad 6 thru_hole oval (at -2.54 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 35 "Net-(J17-Pad22)"))
(pad 7 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 31 "Net-(J17-Pad18)"))
(pad 8 thru_hole oval (at -2.54 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 34 "Net-(J17-Pad21)"))
(pad 9 thru_hole oval (at 0 10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 32 "Net-(J17-Pad19)"))
(pad 10 thru_hole oval (at -2.54 10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 33 "Net-(J17-Pad20)"))
(pad 11 thru_hole oval (at 0 12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 12 thru_hole oval (at -2.54 12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
added components
2020-09-09 20:10:56 +02:00
(pad 13 thru_hole oval (at 0 15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 69 "Net-(C1-Pad1)"))
added components
2020-09-09 20:10:56 +02:00
(pad 14 thru_hole oval (at -2.54 15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 69 "Net-(C1-Pad1)"))
added components
2020-09-09 20:10:56 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_2x07_P2.54mm_Horizontal.wrl
initial commit
2020-08-31 13:01:17 +02:00
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
added components
2020-09-09 20:10:56 +02:00
(module TerminalBlock_TE-Connectivity:TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal (layer F.Cu) (tedit 5B1EC517) (tstamp 5EB87BEF)
(at 167.64 128.905 180)
initial commit
2020-08-31 13:01:17 +02:00
(descr "Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity")
(tags "THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm")
added components
2020-09-09 20:10:56 +02:00
(path /5EBFCB16)
(fp_text reference J5 (at 13.97 8.255) (layer F.SilkS)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_text value "FPGA PIN 25-36" (at 13.335 -4.445) (layer F.Fab)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start 29.94 -3.75) (end -2 -3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.94 3.75) (end 29.94 -3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 3.75) (end 29.94 3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -3.75) (end -2 3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.86 3.61) (end -1.46 3.61) (layer F.SilkS) (width 0.12))
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(fp_circle (center 2.54 0) (end 3.64 0) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 1.1 0) (layer F.Fab) (width 0.1))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 13.97 2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(pad 12 thru_hole circle (at 27.94 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
(pad 11 thru_hole circle (at 25.4 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 61 "Net-(J5-Pad11)"))
(pad 10 thru_hole circle (at 22.86 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 62 "Net-(J5-Pad10)"))
(pad 9 thru_hole circle (at 20.32 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 63 "Net-(J5-Pad9)"))
(pad 8 thru_hole circle (at 17.78 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 64 "Net-(J5-Pad8)"))
(pad 7 thru_hole circle (at 15.24 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 65 "Net-(J5-Pad7)"))
(pad 6 thru_hole circle (at 12.7 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 66 "Net-(J5-Pad6)"))
(pad 5 thru_hole circle (at 10.16 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 67 "Net-(J5-Pad5)"))
(pad 4 thru_hole circle (at 7.62 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 68 "Net-(J5-Pad4)"))
(pad 3 thru_hole circle (at 5.08 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 45 "Net-(J18-Pad15)"))
(pad 2 thru_hole circle (at 2.54 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 46 "Net-(J18-Pad14)"))
(pad 1 thru_hole rect (at 0 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 47 "Net-(J18-Pad13)"))
added components
2020-09-09 20:10:56 +02:00
(model ${KISYS3DMOD}/TerminalBlock_TE-Connectivity.3dshapes/TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
wired everything
2020-09-09 22:16:18 +02:00
(module TerminalBlock_TE-Connectivity:TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal (layer F.Cu) (tedit 5B1EC517) (tstamp 5EB87BA7)
(at 200.025 128.905 180)
added components
2020-09-09 20:10:56 +02:00
(descr "Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity")
(tags "THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm")
wired everything
2020-09-09 22:16:18 +02:00
(path /5EBFAF44)
(fp_text reference J4 (at 13.97 8.255) (layer F.SilkS)
added components
2020-09-09 20:10:56 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
wired everything
2020-09-09 22:16:18 +02:00
(fp_text value "FPGA PIN 37-48" (at 15.24 -4.445) (layer F.Fab)
added components
2020-09-09 20:10:56 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
initial commit
2020-08-31 13:01:17 +02:00
(fp_circle (center 0 0) (end 1.1 0) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_circle (center 2.54 0) (end 3.64 0) (layer F.Fab) (width 0.1))
(fp_circle (center 5.08 0) (end 6.18 0) (layer F.Fab) (width 0.1))
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(fp_line (start -1.86 2.97) (end -1.86 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start -1.86 3.61) (end -1.46 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start -2 -3.75) (end -2 3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 3.75) (end 29.94 3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.94 3.75) (end 29.94 -3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.94 -3.75) (end -2 -3.75) (layer F.CrtYd) (width 0.05))
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at 13.97 2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
wired everything
2020-09-09 22:16:18 +02:00
(pad 1 thru_hole rect (at 0 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 57 "Net-(J18-Pad1)"))
(pad 2 thru_hole circle (at 2.54 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 56 "Net-(J18-Pad2)"))
(pad 3 thru_hole circle (at 5.08 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 55 "Net-(J18-Pad3)"))
(pad 4 thru_hole circle (at 7.62 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 54 "Net-(J18-Pad4)"))
(pad 5 thru_hole circle (at 10.16 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 53 "Net-(J18-Pad5)"))
(pad 6 thru_hole circle (at 12.7 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 52 "Net-(J18-Pad6)"))
(pad 7 thru_hole circle (at 15.24 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 51 "Net-(J18-Pad7)"))
(pad 8 thru_hole circle (at 17.78 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 50 "Net-(J18-Pad8)"))
(pad 9 thru_hole circle (at 20.32 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 49 "Net-(J18-Pad9)"))
(pad 10 thru_hole circle (at 22.86 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 48 "Net-(J18-Pad10)"))
(pad 11 thru_hole circle (at 25.4 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 17 "Net-(J10-Pad4)"))
(pad 12 thru_hole circle (at 27.94 0 180) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 70 "Net-(J18-Pad12)"))
added components
2020-09-09 20:10:56 +02:00
(model ${KISYS3DMOD}/TerminalBlock_TE-Connectivity.3dshapes/TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
wired everything
2020-09-09 22:16:18 +02:00
(module TerminalBlock_TE-Connectivity:TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal (layer F.Cu) (tedit 5EB86CF3) (tstamp 5EB87AF7)
(at 46.99 128.905)
added components
2020-09-09 20:10:56 +02:00
(descr "Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity")
(tags "THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm")
wired everything
2020-09-09 22:16:18 +02:00
(path /5EBF7475)
(fp_text reference J1 (at 13.97 -8.255) (layer F.SilkS)
added components
2020-09-09 20:10:56 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
wired everything
2020-09-09 22:16:18 +02:00
(fp_text value "FPGA PIN 1-12" (at 13.97 4.37) (layer F.Fab)
added components
2020-09-09 20:10:56 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 1.1 0) (layer F.Fab) (width 0.1))
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(fp_line (start -2 -3.75) (end -2 3.75) (layer F.CrtYd) (width 0.05))
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(fp_line (start 29.94 3.75) (end 29.94 -3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.94 -3.75) (end -2 -3.75) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 13.97 2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
wired everything
2020-09-09 22:16:18 +02:00
(pad 1 thru_hole rect (at 0 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 1 "Net-(J1-Pad1)"))
(pad 2 thru_hole circle (at 2.54 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 2 "Net-(J1-Pad2)"))
(pad 3 thru_hole circle (at 5.08 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 3 "Net-(J1-Pad3)"))
(pad 4 thru_hole circle (at 7.62 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 4 "Net-(J1-Pad4)"))
(pad 5 thru_hole circle (at 10.16 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 5 "Net-(J1-Pad5)"))
(pad 6 thru_hole circle (at 12.7 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 6 "Net-(J1-Pad6)"))
(pad 7 thru_hole circle (at 15.24 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 7 "Net-(J1-Pad7)"))
(pad 8 thru_hole circle (at 17.78 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 8 "Net-(J1-Pad8)"))
(pad 9 thru_hole circle (at 20.32 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 9 "Net-(J1-Pad9)"))
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(net 10 "Net-(J1-Pad10)"))
(pad 11 thru_hole circle (at 25.4 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 11 "Net-(J1-Pad11)"))
(pad 12 thru_hole circle (at 27.94 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 12 "Net-(J1-Pad12)"))
(model ${KISYS3DMOD}/TerminalBlock_TE-Connectivity.3dshapes/TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module TerminalBlock_TE-Connectivity:TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal (layer F.Cu) (tedit 5B1EC517) (tstamp 5EB87B3F)
(at 79.375 128.905)
(descr "Terminal Block TE 1-282834-2, 12 pins, pitch 2.54mm, size 30.94x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity")
(tags "THT Terminal Block TE 1-282834-2 pitch 2.54mm size 30.94x6.5mm^2 drill 1.1mm pad 2.1mm")
(path /5EBFA515)
(fp_text reference J2 (at 13.97 -8.255) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "FPGA PIN 13-24" (at 13.97 4.37) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 29.94 -3.75) (end -2 -3.75) (layer F.CrtYd) (width 0.05))
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(fp_line (start -1.86 2.97) (end -1.86 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start 28.641 -0.835) (end 27.106 0.7) (layer F.Fab) (width 0.1))
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(fp_line (start 15.941 -0.835) (end 14.406 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 16.075 -0.7) (end 14.54 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 13.401 -0.835) (end 11.866 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 13.535 -0.7) (end 12 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 10.861 -0.835) (end 9.326 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 10.995 -0.7) (end 9.46 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 8.321 -0.835) (end 6.786 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 8.455 -0.7) (end 6.92 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 5.781 -0.835) (end 4.246 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 5.915 -0.7) (end 4.38 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 3.241 -0.835) (end 1.706 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 3.375 -0.7) (end 1.84 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 0.701 -0.835) (end -0.835 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 0.835 -0.7) (end -0.701 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 29.56 -3.37) (end 29.56 3.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 -3.37) (end -1.62 3.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 3.37) (end 29.56 3.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 -3.37) (end 29.56 -3.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 -2.25) (end 29.56 -2.25) (layer F.SilkS) (width 0.12))
(fp_line (start -1.5 -2.25) (end 29.44 -2.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.62 2.85) (end 29.56 2.85) (layer F.SilkS) (width 0.12))
(fp_line (start -1.5 2.85) (end 29.44 2.85) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 2.85) (end -1.5 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.1 3.25) (end -1.5 2.85) (layer F.Fab) (width 0.1))
(fp_line (start 29.44 3.25) (end -1.1 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 29.44 -3.25) (end 29.44 3.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 -3.25) (end 29.44 -3.25) (layer F.Fab) (width 0.1))
(fp_circle (center 27.94 0) (end 29.04 0) (layer F.Fab) (width 0.1))
(fp_circle (center 25.4 0) (end 26.5 0) (layer F.Fab) (width 0.1))
(fp_circle (center 22.86 0) (end 23.96 0) (layer F.Fab) (width 0.1))
(fp_circle (center 20.32 0) (end 21.42 0) (layer F.Fab) (width 0.1))
(fp_circle (center 17.78 0) (end 18.88 0) (layer F.Fab) (width 0.1))
(fp_circle (center 15.24 0) (end 16.34 0) (layer F.Fab) (width 0.1))
(fp_circle (center 12.7 0) (end 13.8 0) (layer F.Fab) (width 0.1))
(fp_circle (center 10.16 0) (end 11.26 0) (layer F.Fab) (width 0.1))
(fp_circle (center 7.62 0) (end 8.72 0) (layer F.Fab) (width 0.1))
(fp_circle (center 5.08 0) (end 6.18 0) (layer F.Fab) (width 0.1))
(fp_circle (center 2.54 0) (end 3.64 0) (layer F.Fab) (width 0.1))
(fp_circle (center 0 0) (end 1.1 0) (layer F.Fab) (width 0.1))
(fp_text user %R (at 13.97 2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
initial commit
2020-08-31 13:01:17 +02:00
(pad 12 thru_hole circle (at 27.94 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(pad 11 thru_hole circle (at 25.4 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 36 "Net-(J17-Pad23)"))
(pad 10 thru_hole circle (at 22.86 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 35 "Net-(J17-Pad22)"))
(pad 9 thru_hole circle (at 20.32 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 34 "Net-(J17-Pad21)"))
(pad 8 thru_hole circle (at 17.78 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 33 "Net-(J17-Pad20)"))
(pad 7 thru_hole circle (at 15.24 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 32 "Net-(J17-Pad19)"))
(pad 6 thru_hole circle (at 12.7 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 31 "Net-(J17-Pad18)"))
(pad 5 thru_hole circle (at 10.16 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 30 "Net-(J17-Pad17)"))
(pad 4 thru_hole circle (at 7.62 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 29 "Net-(J17-Pad16)"))
(pad 3 thru_hole circle (at 5.08 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 28 "Net-(J17-Pad15)"))
(pad 2 thru_hole circle (at 2.54 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 27 "Net-(J17-Pad14)"))
(pad 1 thru_hole rect (at 0 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
(net 26 "Net-(J17-Pad13)"))
(model ${KISYS3DMOD}/TerminalBlock_TE-Connectivity.3dshapes/TerminalBlock_TE_1-282834-2_1x12_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module TerminalBlock_TE-Connectivity:TerminalBlock_TE_282834-2_1x02_P2.54mm_Horizontal (layer F.Cu) (tedit 5B1EC513) (tstamp 5EB87B5F)
(at 52.705 22.225)
(descr "Terminal Block TE 282834-2, 2 pins, pitch 2.54mm, size 5.54x6.5mm^2, drill diamater 1.1mm, pad diameter 2.1mm, see http://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F282834%7FC1%7Fpdf%7FEnglish%7FENG_CD_282834_C1.pdf, script-generated using https://github.com/pointhi/kicad-footprint-generator/scripts/TerminalBlock_TE-Connectivity")
(tags "THT Terminal Block TE 282834-2 pitch 2.54mm size 5.54x6.5mm^2 drill 1.1mm pad 2.1mm")
(path /5EBFFD2E)
(fp_text reference J3 (at 1.27 -4.37) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
initial commit
2020-09-09 10:09:40 +02:00
(fp_text value "Power Supply" (at 1.27 5.08) (layer F.SilkS)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_circle (center 0 0) (end 1.1 0) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_circle (center 2.54 0) (end 3.64 0) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 -3.25) (end 4.04 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 -3.25) (end 4.04 3.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.04 3.25) (end -1.1 3.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.1 3.25) (end -1.5 2.85) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 2.85) (end -1.5 -3.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 2.85) (end 4.04 2.85) (layer F.Fab) (width 0.1))
(fp_line (start -1.62 2.85) (end 4.16 2.85) (layer F.SilkS) (width 0.12))
(fp_line (start -1.5 -2.25) (end 4.04 -2.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.62 -2.25) (end 4.16 -2.25) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 -3.37) (end 4.16 -3.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 3.37) (end 4.16 3.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.62 -3.37) (end -1.62 3.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.16 -3.37) (end 4.16 3.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.835 -0.7) (end -0.701 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 0.701 -0.835) (end -0.835 0.7) (layer F.Fab) (width 0.1))
(fp_line (start 3.375 -0.7) (end 1.84 0.835) (layer F.Fab) (width 0.1))
(fp_line (start 3.241 -0.835) (end 1.706 0.7) (layer F.Fab) (width 0.1))
(fp_line (start -1.86 2.97) (end -1.86 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start -1.86 3.61) (end -1.46 3.61) (layer F.SilkS) (width 0.12))
(fp_line (start -2 -3.75) (end -2 3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 3.75) (end 4.54 3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.54 3.75) (end 4.54 -3.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.54 -3.75) (end -2 -3.75) (layer F.CrtYd) (width 0.05))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 1.27 2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(pad 2 thru_hole circle (at 2.54 0) (size 2.1 2.1) (drill 1.1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/TerminalBlock_TE-Connectivity.3dshapes/TerminalBlock_TE_282834-2_1x02_P2.54mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C1F)
(at 185.42 19.685 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA62A6)
(fp_text reference J8 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX1 DI DE RE RO" (at 3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 14 "Net-(J8-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 47 "Net-(J18-Pad13)"))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C37)
(at 168.91 19.685 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA7AB2)
(fp_text reference J9 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX2 DI DE RE RO" (at 3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 "Net-(J9-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 70 "Net-(J18-Pad12)"))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C4F)
(at 152.4 19.685 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA903B)
(fp_text reference J10 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX3 DI DE RE RO" (at 3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 16 "Net-(J10-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 "Net-(J10-Pad4)"))
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C67)
(at 201.93 60.325 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA477C)
(fp_text reference J11 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX0 VCC B A GND" (at -3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 18 "Net-(J11-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 19 "Net-(J11-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C7F)
(at 185.42 60.325 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA6DA2)
(fp_text reference J12 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX1 VCC B A GND" (at -3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 20 "Net-(J12-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 "Net-(J12-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87C97)
(at 168.91 60.325 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA85AD)
(fp_text reference J13 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX2 VCC B A GND" (at -3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
added components
2020-09-09 20:10:56 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
initial commit
2020-08-31 13:01:17 +02:00
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 22 "Net-(J13-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 "Net-(J13-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x04_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A429) (tstamp 5EB87CAF)
(at 152.4 60.325 270)
(descr "Through hole straight socket strip, 1x04, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x04 2.54mm single row")
(path /5EBA980F)
(fp_text reference J14 (at 0 -2.77 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "DMX3 VCC B A GND" (at -3.81 3.81) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.8 9.4) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.75 9.4) (end -1.8 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 8.95) (end 1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 8.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 8.89) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 8.89) (end -1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 8.89) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 3.81) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 24 "Net-(J14-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 25 "Net-(J14-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 58 +5V))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x04_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Connector_PinSocket_2.54mm:PinSocket_1x24_P2.54mm_Vertical (layer F.Cu) (tedit 5A19A427) (tstamp 5EB87D07)
(at 131.445 65.405)
(descr "Through hole straight socket strip, 1x24, 2.54mm pitch, single row (from Kicad 4.0.7), script generated")
(tags "Through hole socket strip THT 1x24 2.54mm single row")
(path /5EBF1AD7)
(fp_text reference J18 (at 0 -2.77) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "CMOD A7 J2" (at 0 61.19) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
added components
2020-09-09 20:10:56 +02:00
(fp_line (start -1.8 60.2) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
wired everything
2020-09-09 22:16:18 +02:00
(fp_line (start 1.75 60.2) (end -1.8 60.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.8) (end 1.75 60.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end 1.75 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 0 -1.33) (end 1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -1.33) (end 1.33 0) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 59.75) (end 1.33 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 59.75) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 59.69) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 59.69) (end -1.27 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.635) (end 1.27 59.69) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -1.27) (end 1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end 0.635 -1.27) (layer F.Fab) (width 0.1))
initial commit
2020-08-31 13:01:17 +02:00
(fp_text user %R (at 0 29.21 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 24 thru_hole oval (at 0 58.42) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 59 GND))
initial commit
2020-08-31 13:01:17 +02:00
(pad 23 thru_hole oval (at 0 55.88) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 37 "Net-(J18-Pad23)"))
(pad 22 thru_hole oval (at 0 53.34) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 38 "Net-(J18-Pad22)"))
(pad 21 thru_hole oval (at 0 50.8) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 39 "Net-(J18-Pad21)"))
(pad 20 thru_hole oval (at 0 48.26) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 40 "Net-(J18-Pad20)"))
(pad 19 thru_hole oval (at 0 45.72) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 41 "Net-(J18-Pad19)"))
(pad 18 thru_hole oval (at 0 43.18) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 42 "Net-(J18-Pad18)"))
(pad 17 thru_hole oval (at 0 40.64) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 43 "Net-(J18-Pad17)"))
(pad 16 thru_hole oval (at 0 38.1) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 44 "Net-(J18-Pad16)"))
(pad 15 thru_hole oval (at 0 35.56) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 45 "Net-(J18-Pad15)"))
(pad 14 thru_hole oval (at 0 33.02) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 46 "Net-(J18-Pad14)"))
(pad 13 thru_hole oval (at 0 30.48) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 47 "Net-(J18-Pad13)"))
(pad 12 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 70 "Net-(J18-Pad12)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 11 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 17 "Net-(J10-Pad4)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 48 "Net-(J18-Pad10)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 49 "Net-(J18-Pad9)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 50 "Net-(J18-Pad8)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 51 "Net-(J18-Pad7)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 52 "Net-(J18-Pad6)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 53 "Net-(J18-Pad5)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 54 "Net-(J18-Pad4)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 55 "Net-(J18-Pad3)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 56 "Net-(J18-Pad2)"))
initial commit
2020-08-31 13:01:17 +02:00
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
wired everything
2020-09-09 22:16:18 +02:00
(net 57 "Net-(J18-Pad1)"))
initial commit
2020-08-31 13:01:17 +02:00
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x24_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
initial commit
2020-09-09 10:09:40 +02:00
(gr_text JLCJLCJLCJLC (at 123.825 128.905) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
initial commit
2020-08-31 13:01:17 +02:00
(gr_text "Strip 1-8 on Pin 26-33 Universe 1001 - 1008\nDMX 1-4 via MAX485 Universe 1-4" (at 73.66 99.06) (layer F.SilkS)
(effects (font (size 2 1.75) (thickness 0.15)))
)
(gr_text "P&M GbR\nArt-Net to 8x WS2812B + 4x DMX" (at 73.66 81.28) (layer F.SilkS)
(effects (font (size 2.5 2.5) (thickness 0.15)))
)
initial commit
2020-09-09 10:09:40 +02:00
(gr_text "3.3V\n\nGND\n\nMDIO MDC\n\nCLK CRS\n\nRX0 RX1\n\nTX_EN TX0\n\nTX1 NC" (at 87.63 36.83 90) (layer F.SilkS)
initial commit
2020-08-31 13:01:17 +02:00
(effects (font (size 0.75 1) (thickness 0.15)))
)
(gr_text "GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48" (at 168.91 123.825) (layer F.SilkS)
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initial commit
2020-08-31 13:01:17 +02:00
wired everything
2020-09-09 22:16:18 +02:00
(zone (net 58) (net_name +5V) (layer B.Cu) (tstamp 5F4E5608) (hatch edge 0.508)
initial commit
2020-08-31 13:01:17 +02:00
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2020-09-09 20:10:56 +02:00
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2020-09-09 22:16:18 +02:00
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initial commit
2020-09-09 10:09:40 +02:00
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wired everything
2020-09-09 22:16:18 +02:00
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added components
2020-09-09 20:10:56 +02:00
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wired everything
2020-09-09 22:16:18 +02:00
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